CHIP-8

Memory-Mapped Register Architecture

▶ LOAD ROM

SPEED 11

PC: 0xEE4+0 bytes (0x200) I: 0x000 SP: 0x00 DT: 0 ST: 0 OP: 0000 ♪

Theme: Scanlines Debug Panel

Memory-Mapped Registers (0xEA0–0xEE6)

FNT

PROGRAM ROM

REG

V-Registers (0xED0–0xEDF)

Scalar Registers

Call Stack (0xEA0–0xECF)

Hex Dump (0xEA0–0xEE6)

About Memory-Mapped Architecture

This CHIP-8 emulator uses a memory-mapped register architecture where all CPU state resides within the main 4KB memory space at offset 0xEA0.

Register Layout:

Call Stack (0xEA0–0xECF): 48 bytes, 12 levels × 2 bytes each
V-Registers (0xED0–0xEDF): 16 bytes, V0–VF
I Register (0xEE0–0xEE1): 2 bytes, 16-bit index
Delay Timer (0xEE2): 1 byte, decrements at 60Hz
Sound Timer (0xEE3): 1 byte, decrements at 60Hz
Program Counter (0xEE4–0xEE5): 2 bytes
Stack Pointer (0xEE6): 1 byte

Because registers live in memory, programs can inspect or manipulate their own CPU state through normal memory access instructions (FX55/FX65). If I is set to point at the register block, you can read/write registers directly!

Keyboard mapping: 1234 / QWER / ASDF / ZXCV → CHIP-8 keys 123C / 456D / 789E / A0BF